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810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 1 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary g eneral d escription the ICS810001-21 is a member of the hiperclocks? family of high performance clock solutions from ics. the ICS810001-21 is a pll based synchronous clock generator that is optimized for digital video clock jitter attenuation and frequency translation. the device contains two internal frequency multiplication stages that are cascaded in series. the first stage is a vcxo pll that is optimized to provide reference clock jitter attenuation, and to support the complex pll multiplication ratios needed for video rate conversion. the second stage is a femtoclock frequency multiplier that provides the low jitter, high frequency video output clock. preset multiplication ratios are selected from internal lookup tables using device input selection pins. the multiplication ra- tios are optimized to support most common video rates used in professional video system applications. the vcxo requires the use of an external, inexpensive pullable crystal. two crys- tal connections are provided (pin selectable) so that both 60 and 59.94 base frame rates can be supported. the vcxo re- quires external passive loop filter components which are used to set the pll loop bandwidth and damping characteristics. p in a ssignment hiperclocks? ic s f eatures ? accepts various hd and sd references including hsync, transport and pixel clock rates ? outputs hd and sd pixel rates ? one lvcmos/lvttl pll clock output ? two selectable lvcmos/lvttl input clocks ? lvcmos input select lines ? vcxo pll bandwidth can be optimized for jitter attenuation and reference tracking ? femtoclock frequency multiplier provides low jitter, high frequency output ? femtoclock range: 560mhz - 700mhz ? rms phase jitter @148.3516484mhz, using a 26.973027mhz crystal (12khz - 20mhz): 0.81ps (typical) ? 3.3v supply voltage ? 0c to 70c ambient operating temperature 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 n0 n1 nbp1 oe gnd q v ddo v dda ICS810001-21 clk0 v0 v dd mr mf v1 v2 v3 v dd xtal_sel xtal_out1 xtal_in1 gnd xtal_out0 xtal_in0 v ddx lf1 lf0 iset v dd nbp0 gnd clk_sel clk1 32-lead vfqfn 5mm x 5mm x 0.95 package body k package top view o utput r ates s upported : ) z h m ( y c n e u q e r fn o i t a c i l p p a z h m 7 26 5 6 r i c c , 1 0 6 r - u t i , t r o p s n a r t g e p m z h m 7 2 0 3 7 9 . 6 21 0 0 1 / 0 0 0 1 x z h m 7 2 z h m 5 2 . 4 70 6 / m 2 9 2 e t p m s z h m 8 1 4 2 8 5 7 1 . 4 74 9 . 9 5 / m 2 9 2 e t p m s z h m 5 . 8 4 1p 0 8 0 1 , 0 6 / m 2 9 2 e t p m s z h m 4 8 4 6 1 5 3 . 8 4 1p 0 8 0 1 , 4 9 . 9 5 / m 2 9 2 e t p m s z h m 6 3? d ? l e v e l m 9 5 2 e t p m s e xample f requency c onversions : all nine combinations from / to: 27mhz 74.175mhz 74.25mhz ntsc or pal hsync to 27mhz ntsc or pal hsync to 4xfsc the preliminary information presented herein represents a product in prototyping or pre-production. the noted characteristics a re based on initial product characterization. integrated circuit systems, incorporated (ics) reserves the right to change any circuitry or specific ations without notice.
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 2 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary b lock d iagram charge pump vcxo v3:v0 phase detector q output divider 00 = 4 01 = 8 10 = 12 11 = 18 vcxo feedback divider (m value from table) vcxo input pre-divider (p value from table) vcxo jitter attenuation pll xtal_in0 xtal_out0 xtal_in1 xtal_out1 lf1 lf0 iset loop filter vcxo divider table oe xtal_sel 01 mf mr master reset 0 1 clk0 clk1 clk_sel n1:n0 4 2 11 10 10 11 01 01 10 11 00 2 nbp1:nbp0 femtoclock frequency multiplier 0= x22 1= x24
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 3 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p ) t u p t u o r e p ( v d d v , a d d v , o d d v 5 6 4 . 3 =d b tf p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 10 f l , 1 f l g o l a n a t u p t u o / t u p n i . s n i p e d o n n o i t c e n n o c r e t l i f p o o l 3t e s i g o l a n a t u p t u o / t u p n i . n i p g n i t t e s t n e r r u c p m u p e g r a h c 5 2 , 1 1 , 4v d d r e w o p. s n i p y l p p u s r e w o p e r o c 2 2 , 5 , 0 p b n 1 p b n t u p n ip u l l u p. m a r g a i d k c o l b e e s . s n i p l o r t n o c s s a p y b l l p 9 2 , 0 2 , 6d n gr e w o p. d n u o r g y l p p u s r e w o p 7l e s _ k l ct u p n in w o d l l u p s t c e l e s , w o l n e h w . 1 k l c s t c e l e s h g i h n e h w . t c e l e s k c o l c t u p n i . s l e v e l e c a f r e t n i l t t v l / s o m c v l . 0 k l c 9 , 80 k l c , 1 k l ct u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . s t u p n i k c o l c , 4 1 , 0 1 6 1 , 5 1 , 1 v , 0 v 3 v , 2 v t u p n in w o d l l u p . s l e v e l e c a f r e t n i l t t v l / s o m c v l . s n i p n o i t c e l e s r e d i v i d l l p o x c v 2 1r mt u p n in w o d l l u p s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a e h t , w o l c i g o l n e h w . w o l o g o t t u p t u o e h t g n i s u a c t e s e r e r a . d e l b a n e s i t u p t u o e h t d n a s r e d i v i d l a n r e t n i . s l e v e l e c a f r e t n i l t t v l / s o m c v l 3 1f mt u p n in w o d l l u p . n i p t c e l e s r o t c a f n o i t a c i l p i t l u m k c o l c o t m e f . s l e v e l e c a f r e t n i l t t v l / s o m c v l 7 1v a d d r e w o p. n i p y l p p u s g o l a n a 8 1v o d d r e w o p. n i p y l p p u s r e w o p t u p t u o 9 1q t u p t u o . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p t u o k c o l c l l p o x c v 1 2e ot u p n ip u l l u p . e t a t s i r t n i s i t u p t u o k c o l c e h t , w o l c i g o l n e h w . e l b a n e t u p t u o . d e l b a n e s i t u p t u o e h t , h g i h c i g o l n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l 4 2 , 3 20 n , 1 nt u p n in w o d l l u p . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t c e l e s e d i v i d t u p t u o k c o l c o t m e f 6 2l e s _ l a t xt u p n in w o d l l u p s t c e l e s , w o l n e h w . 1 l a t x s t c e l e s , h g i h n e h w . t c e l e s l a t s y r c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . 0 l a t x , 7 2 8 2 , 1 t u o _ l a t x 1 n i _ l a t x t u p n i . t u p n i e h t s i 1 n i _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c . t u p t u o e h t s i 1 t u o _ l a t x , 0 3 1 3 , 0 t u o _ l a t x 0 n i _ l a t x t u p n i . t u p n i e h t s i 0 n i _ l a t x . e c a f r e t n i r o t a l l i c s o l a t s y r c . t u p t u o e h t s i 0 t u o _ l a t x 2 3v x d d r e w o p. p m u p e g r a h c o x c v r o f n i p y l p p u s r e w o p : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 4 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary e l b a t p u - k o o l r e d i v i d l l p o x c vn o i t a c i l p p a k c o l c o e d i vn o i t a c i l p p a k c o l c o e d i v e t a n r e t l a s n i p 0 v : 3 ve u l a v pe u l a v m) z h m / z h k ( t u p n i) z h m ( o x c v) z h m / z h k ( t u p n i) z h m ( o x c v 0 0 0 00 0 0 10 0 0 1z h m 7 2z h m 7 2z h m 3 7 9 . 6 2z h m 3 7 9 . 6 2 1 0 0 01 0 0 10 0 0 1z h m 7 2z h m 3 7 9 . 6 2 0 1 0 00 0 0 1 14 0 0 4z h m 5 7 1 . 4 7z h m 7 2 1 1 0 01 1 0 1 10 0 0 4z h m 5 2 . 4 7z h m 3 7 9 . 6 2 0 0 1 00 0 0 1 10 0 0 4z h m 5 2 . 4 7z h m 7 2 1 0 1 04 0 0 44 0 0 4z h m 7 2z h m 7 2z h m 3 7 9 . 6 2z h m 3 7 9 . 6 2 0 1 1 04 0 0 40 0 0 4z h m 7 2z h m 3 7 9 . 6 2 1 1 1 00 0 0 11 0 0 1z h m 3 7 9 . 6 2z h m 7 2 0 0 0 10 5 21 9z h m 5 7 1 . 4 7z h m 7 2 1 0 0 13 5 22 9z h m 5 2 . 4 7z h m 7 2 0 1 0 12 92 9z h m 7 2z h m 7 2z h m 3 7 9 . 6 2z h m 3 7 9 . 6 2 1 1 0 110 0 6 z h k 5 4 ) c n y s h 0 6 / p 0 2 7 ( z h m 7 2 z h k 5 5 9 . 4 4 ) 4 9 . 9 5 / p 0 2 7 ( z h m 3 7 9 . 6 2 0 0 1 110 0 8 z h k 5 7 . 3 3 ) c n y s h 0 6 / i 0 8 0 1 ( z h m 7 2 z h k 6 1 7 . 3 3 ) 4 9 . 9 5 / i 0 8 0 1 ( z h m 3 7 9 . 6 2 1 0 1 118 2 7 1 z h k 5 2 6 . 5 1 ) c n y s h l a p ( z h m 7 2 0 1 1 116 1 7 1 z h k 4 3 7 . 5 1 ) c n y s h c s t n ( z h m 7 2 1 1 1 110 6 9 z h k 5 2 1 . 8 2 ) c n y s h 0 5 / i 0 8 0 1 ( z h m 7 2 t able 3a. f irst f requency t ranslation s tage : vcxo pll t able 3c. b ypass f unction t able s t u p n i n o i t a r e p o 1 p b n0 p b n 00 r e d i v i d t u p t u o d n a l l p r o t a l s n a r t y c n e u q e r f s s a p y b 01 l l p r o t a l s n a r t y c n e u q e r f d n a l l p n o i t a u n e t t a r e t t i j o x c v s s a p y b : e d o m t s e t 10 l l p n o i t a u n e t t a r e t t i j o x c v s s a p y b : e d o m c l 11 e v i t c a : e d o m l l p e l b a t p u - k o o l k c o l c o t m e fn o i t a c i l p p a k c o l c o e d i vn o i t a c i l p p a k c o l c o e d i v e t a n r e t l a s n i p 0 n : 1 n , f mv i d b fv i d t u o) z h m ( o x c v) z h m ( q) z h m ( o x c v) z h m ( q 0 0 , 02 24 z h m 7 2z h m 5 . 8 4 1z h m 3 7 9 . 6 2z h m 5 3 . 8 4 1 1 0 , 02 28 z h m 7 2z h m 5 2 . 4 7z h m 3 7 9 . 6 2z h m 5 7 1 . 4 7 0 1 , 02 22 1 1 1 , 02 28 1 0 0 , 14 24 1 0 , 14 28 0 1 , 14 22 1z h m 7 2z h m 4 5 1 1 , 14 28 1z h m 7 2z h m 6 3 t able 3b. s econd f requency t ranslation s tage : f emto c lock m ultiplier
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 5 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary t able 3d. e xample f requency c onfiguration t able , continued on next page n o i t a r u g i f n o c e l p m a x e r e b m u n t u p n i e c n e r e f e r y c n e u q e r f ) z h m ( e c n e r e f e r k c o l c n o i t p i r c s e d l l p o x c vl l p k c o l c o t m e f l e s _ o c v t u p t u o y c n e u q e r f ) z h m (n o i t p i r c s e d t u p t u o p t u p n i r e d i v i d m k c a b d e e f r e d i v i d l a t x y c n e u q e r f ) z h m ( f m k c a b d e e f r e d i v i d n t u p t u o r e d i v i d 17 2t r o p s n a r t1 0 0 10 0 0 17 2 0 3 7 9 . 6 22 281 8 1 4 2 8 5 7 1 . 4 74 9 . 9 5 / m 2 9 2 e t p m s 27 2t r o p s n a r t0 0 0 10 0 0 17 22 281 5 2 . 4 70 6 / m 2 9 2 e t p m s 37 2t r o p s n a r t1 0 0 10 0 0 17 2 0 3 7 9 . 6 22 241 4 8 4 6 1 5 3 . 8 4 1) p 0 8 0 1 ( 4 9 . 9 5 / m 2 9 2 e t p m s 47 2t r o p s n a r t0 0 0 10 0 0 17 22 241 5 . 8 4 1) p 0 8 0 1 ( 0 6 / m 2 9 2 e t p m s 57 2t r o p s n a r t1 0 0 10 0 0 17 2 0 3 7 9 . 6 2a na n0 7 2 0 3 7 9 . 6 21 0 0 1 / 0 0 0 1 x t r o p s n a r t 67 2t r o p s n a r t0 0 0 10 0 0 17 2a na n0 7 2t r o p s n a r t 0 14 2 8 5 7 1 . 4 74 9 . 9 5 / m 2 9 20 0 0 1 14 0 0 47 22 281 5 2 . 4 70 6 / m 2 9 2 e t p m s 1 15 2 . 4 70 6 / m 2 9 21 1 0 1 10 0 0 47 2 0 3 7 9 . 6 22 281 8 1 4 2 8 5 7 1 . 4 74 9 . 9 5 / m 2 9 2 e t p m s 2 14 2 8 5 7 1 . 4 74 9 . 9 5 / m 2 9 20 0 0 1 10 0 0 47 2 0 3 7 9 . 6 22 281 8 1 4 2 8 5 7 1 . 4 74 9 . 9 5 / m 2 9 2 e t p m s 3 15 2 . 4 70 6 / m 2 9 20 0 0 1 10 0 0 47 22 281 5 2 . 4 70 6 / m 2 9 2 e t p m s 4 14 2 8 5 7 1 . 4 74 9 . 9 5 / m 2 9 20 0 0 1 14 0 0 47 2a na n0 7 2t r o p s n a r t 5 15 2 . 4 70 6 / m 2 9 20 0 0 1 10 0 0 47 2a na n0 7 2t r o p s n a r t 6 17 2t r o p s n a r t4 0 0 44 0 0 47 2a na n0 7 2t r o p s n a r t 7 17 2t r o p s n a r t4 0 0 40 0 0 47 2 0 3 7 9 . 6 22 281 8 1 4 2 8 5 7 1 . 4 74 9 . 9 5 / m 2 9 2 e t p m s 8 17 2t r o p s n a r t4 0 0 44 0 0 47 22 281 5 2 . 4 7b d h 0 24 2 8 5 7 1 . 4 74 9 . 9 5 / m 2 9 20 5 21 97 22 281 5 2 . 4 70 6 / m 2 9 2 e t p m s 1 25 2 . 4 70 6 / m 2 9 23 5 22 97 22 281 5 2 . 4 7) p 0 8 0 1 ( 0 6 / m 2 9 2 e t p m s 2 24 2 8 5 7 1 . 4 74 9 . 9 5 / m 2 9 23 5 22 97 2 0 3 7 9 . 6 22 281 8 1 4 2 8 5 7 1 . 4 74 9 . 9 5 / m 2 9 2 e t p m s 3 27 2t r o p s n a r t2 92 97 22 281 5 2 . 4 70 6 / m 2 9 2 e t p m s 0 34 2 8 5 7 1 . 4 74 9 . 9 5 / m 2 9 20 5 21 97 2a na n0 7 2t r o p s n a r t 1 35 2 . 4 70 6 / m 2 9 23 5 22 97 2a na n0 7 2t r o p s n a r t 2 35 2 . 4 70 6 / m 2 9 21 1 0 1 10 0 0 47 2 0 3 7 9 . 6 2a na n0 7 2 0 3 7 9 . 6 21 0 0 1 / 0 0 0 1 x t r o p s n a r t 3 34 2 8 5 7 1 . 4 74 9 . 9 5 / m 2 9 23 5 22 97 2 0 3 7 9 . 6 2a na n0 7 2 0 3 7 9 . 6 21 0 0 1 / 0 0 0 1 x t r o p s n a r t 0 47 2t r o p s n a r t2 92 97 24 22 11 4 5e l p m a s r e v o 6 5 6 / 1 0 6 r - u t i 1 47 2t r o p s n a r t2 92 97 24 28 11 6 3e l p m a s r e v o " d " l e v e l m 9 5 2 2 47 2t r o p s n a r t4 0 0 44 0 0 47 24 28 11 6 3e l p m a s r e v o " d " l e v e l m 9 5 2
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 6 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary t able 3d. e xample f requency c onfiguration t able n o i t a r u g i f n o c e l p m a x e r e b m u n t u p n i e c n e r e f e r y c n e u q e r f ) z h m ( e c n e r e f e r k c o l c n o i t p i r c s e d l l p o x c vl l p k c o l c o t m e f l e s _ o c v t u p t u o y c n e u q e r f ) z h m (n o i t p i r c s e d k c o l c t u p t u o p t u p n i r e d i v i d m k c a b d e e f r e d i v i d l a t x y c n e u q e r f ) z h m ( c f k c a b d e e f r e d i v i d n t u p t u o r e d i v i d 0 51 f2 92 91 fa na n0 1 fz h m 0 3 o t 5 1 = 1 f 0 65 2 6 5 1 0 . 0c n y s h l a p15 3 1 15 3 7 . 7 1a na n0 5 3 7 . 7 1) c s f x 4 ( r e i r r a c b u s l a p x 4 1 64 3 7 5 1 0 . 0c n y s h c s t n10 1 98 1 8 1 3 . 4 1a na n0 8 1 8 1 3 . 4 1) c s f x 4 ( r e i r r a c b u s c s t n x 4 2 65 2 6 5 1 0 . 0c n y s h l a p18 2 7 17 2a na n0 7 2t r o p s n a r t 3 64 3 7 5 1 0 . 0c n y s h c s t n16 1 7 17 2a na n0 7 2t r o p s n a r t 4 65 2 6 5 1 0 . 0c n y s h l a p18 2 7 17 24 22 11 4 5e l p m a s r e v o 6 5 6 / 1 0 6 r - u t i 5 64 3 7 5 1 0 . 0c n y s h c s t n16 1 7 17 24 22 11 4 5e l p m a s r e v o 6 5 6 / 1 0 6 r - u t i
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 7 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary t able 4a. p ower s upply dc c haracteristics , v dd = v dda = v ddo = v ddx = 3.3v5%, t a = 0c to 70c t able 4b. lvcmos / lvttl dc c haracteristics , v dd = v dda = v ddo = v ddx = 3.3v5%, t a = 0c to 70c note 1: outputs terminated with 50 to v ddo /2. a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 34.8c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a d d e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v o d d e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v v x d d e g a t l o v y l p p u s p m u p e g r a h c 5 3 1 . 33 . 35 6 4 . 3v i d d t n e r r u c y l p p u s r e w o p 0 1 2a m i a d d t n e r r u c y l p p u s g o l a n a 0 1a m i o d d t n e r r u c y l p p u s t u p t u o 5a m i x d d t n e r r u c y l p p u s p m u p e g r a h c d b ta m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i t u p n ie g a t l o v h g i h0 . 3v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t u p n i t n e r r u c h g i h , f m , r m , 1 k l c , 0 k l c , 0 : 1 n , 0 : 3 v , 0 p : 1 p l e s _ l a t x , l e s _ k l c v d d v = n i v 5 6 4 . 3 =0 5 1a 1 p b n , 0 p b n , e ov d d v = n i v 5 6 4 . 3 =5a i l i t u p n i t n e r r u c w o l , f m , r m , 1 k l c , 0 k l c , 0 : 1 n , 0 : 3 v , 0 p : 1 p l e s _ l a t x , l e s _ k l c v d d v , v 5 6 4 . 3 = n i v 0 =5 -a 1 p b n , 0 p b n , e ov d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 6 . 2v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 . 0v
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 8 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary t able 5. c rystal c haracteristics r e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u n o i t a l l i c s o f o e d o m l a t n e m a d n u f y c n e u q e r f 4 15 3z h m ) r s e ( e c n a t s i s e r s e i r e s t n e l a v i u q e 0 5 e c n a t i c a p a c t n u h s 7f p k o x c v o c v k ( o x c v 1 e t o n ; ) 0 0 0 7v / z h f ( e g n a r l l u p y c n e u q e r f p 1 e t o n ; ) 0 0 1m p p l e v e l e v i r d 1w m . e c i v e d l a t s y r c z t r a u q d e d n e m m o c e r s c i n a g n i s u n e h w d e e t n a r a u g y l n o e r a s r e t e m a r a p e s e h t : 1 e t o n . s n o i t a d n e m m o c e r e c i v e d l a t s y r c z t r a u q g n i d r a g e r s c i t c a t n o c t able 6. ac c haracteristics , v dd = v dda = v ddo = v ddx = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f t u o y c n e u q e r f t u p t u o 0 0 = 1 p b n , 0 p b n4 15 3z h m 1 = 1 p b n1 35 7 1z h m t ) ? ( t i j , ) m o d n a r ( , r e t t i j e s a h p s m r ; d 3 e l b a t f o 3 n o i t a r u g i f n o c 1 e t o n , z h m 4 8 4 6 1 5 3 . 8 4 1 ) z h m 0 2 - z h k 2 1 : e g n a r n o i t a r g e t n i ( 1 8 . 0s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 5 4s p c d oe l c y c y t u d t u p t u o 0 5% . n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e e s . t o l p e s i o n e s a h p e h t o t r e f e r e s a e l p : 1 e t o n
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 9 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary t ypical p hase n oise at 148.3516484mh z 148.3516484mhz rms phase noise jitter 12k to 20mhz = 0.81ps (typical) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1m 10m 100m o ffset f requency (h z ) p hase n oise ( dbc ) h z phase noise result by adding fibre channel filter to raw data raw phase noise data fibre channel filter ? ? ?
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 10 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary p arameter m easurement i nformation o utput d uty c ycle /p ulse w idth /tp eriod p hase j itter 3.3v o utput l oad ac t est c ircuit scope qx lvcmos 1.65v5% o utput r ise /f all t ime -1.65v5% clock outputs 20% 80% 80% 20% t r t f t period t pw t period odc = v ddo 2 x 100% t pw q v ee v dd , v dda , v ddo, v ddx phase noise mas k offset frequency f 1 f 2 phase noise plot rms jitter = area under the masked phase noise plot noise power
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 11 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary a pplication i nformation r e d i v i d l l p o x c v n o i t c e l e s n o i t c e l e s t n e n o p m o c r e t l i f p o o le c n a m r o f r e p l l p o x c v r e t l i f p o o l e l p m a x e r e b m u n ) e u l a v m ( r e d i v i d b f t e s r k ( ) t e s i ) a ( s r k ( ) s c ) f ( p c ) f p ( l l p o x c v ) b d 3 - / z h ( w b p o o l r o t c a f g n i p m a d 1 0 0 1 , 0 0 0 1 2 . 20 0 51 6 23 3 0 . 00 0 5 10 0 24 . 11 4 . 40 5 21 6 28 6 0 . 00 0 3 30 0 14 . 12 4 . 40 5 26 . 3 55 . 10 0 0 8 60 24 . 13 1 0 0 4 , 0 0 0 4 2 . 20 0 59 9 43 3 0 . 00 0 5 10 0 13 . 14 2 . 20 0 51 6 25 1 . 00 0 8 60 55 . 15 2 . 20 0 55 0 11 0 0 0 3 30 26 . 16 2 9 , 1 94 . 40 5 22 . 3 21 0 0 0 3 30 0 16 . 17 0 0 6 4 . 40 5 21 6 28 6 0 . 00 0 2 2 0 7 18 . 1 8 0 0 85 2 16 . 1 0 6 95 0 15 . 1 0 0 0 1 , 0 0 0 10 0 14 . 1 8 2 7 1 , 6 2 7 18 51 4 0 0 4 , 0 0 0 47 27 . 0 8 2 7 1 , 6 2 7 12 . 20 0 50 0 0 11 0 . 00 7 40 0 15 . 19 e xample l oop f ilter c omponent v alues for v arious vcxo d ivider s elections
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 12 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary a pplication e xample 1: 27mh z to 74.25mh z charge pump vcxo v3:v0 = 0000 phase detector q = 74.25 mhz output divider 00 = 4 01 = 8 10 = 12 11 = 18 vcxo feedback divider = 1000 vcxo input pre-divider = 1000 vcxo jitter attenuation pll xtal_in0 xtal_ out0 xtal_in 1 xtal_ out1 lf1 lf0 iset vcxo divider table oe = 1 xtal_sel = 1 01 mf = 0 mr = 0 master reset 0 1 clk0 = 27 mhz clk1 = gnd clk_sel = 0 n1:n0 = 01 4 2 11 10 10 11 01 01 10 11 00 2 nbp1:nbp0 = 11 femtoclock frequency multiplier = x 22 26.973 mhz 27.000 mhz rset = 4.4k (makes iset = 250 a) cp = 3300 pf cs = 0.068 f rs = 261 k v cxo pll loop characteristics with this configuration: - bandwidth (-3db) = 100 hz - damping factor = 1.4
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 13 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary a pplication e xample 2: 27mh z to 74.175mh z charge pump vcxo v3:v0 = 0001 phase detector q = 74.125 mh z output divider 00 = 4 01 = 8 10 = 12 11 = 18 vcxo feedback divider = 1000 vcxo input pre-divider = 1001 vcxo jitter attenuation pll xtal_in 0 xtal_ out0 xtal_in 1 xtal_ out1 lf1 lf0 iset vcxo divider table oe = 1 xtal_sel = 0 01 mf = 0 mr = 0 master reset 0 1 clk0 = 27 mhz clk1 = gnd clk_sel = 0 n1:n0 = 01 4 2 11 10 10 11 01 01 10 11 00 2 nbp1:nbp0 = 11 femtoclock frequency multiplier = x 22 26.973 mhz 27.000 mhz v cxo pll loop characteristics with this configuration: - bandwidth (-3db) = 100 hz - damping factor = 1.4 rset = 4.4k (makes iset = 250 a) cp = 3300 pf cs = 0.068 f rs = 261 k
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 14 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary d escription of the pll s tages the ics843002-21 is a two stage device, a vcxo pll fol- lowed by a low phase noise femtoclock frequency multiplier. the vcxo uses an external pullable crystal which can be pulled 100ppm by the vcxo pll circuitry to phase lock it to the input reference frequency. there are two vcxo crystal ports in order to provide vcxo frequency versatility. for hdtv applications, this allows the use of a 26.973027mhz crystal for the generation of 74.175mhz, or a 27.00mhz crystal for the generation of 74.25mhz, for example. the vcxo output frequency can be output directly from the device, or it can be passed to the femtoclock frequency multiplier which will multiply it up to a higher frequency. vcxo pll l oop r esponse c onsiderations loop response characteristics of the vcxo pll is affected by the vcxo feedback divider value (bandwidth and damping factor), and by the external loop filter components (bandwidth, damping factor, and 2 nd frequency response). a practical range of vcxo pll bandwidth is from about 1hz to about 1khz. the setting of vcxo pll bandwidth and damping factor is covered later in this document. a pc based pll bandwidth calculator is also under development. for assistance with loop bandwidth suggestions or value calculation, please contact ics applications. table 3a shows frequency translation configuration examples. note that in the first two v3:v0 selections the vcxo pll feed- back divider is the same value of 1000. this means the vcxo pll loop response (bandwidth and damping factor) will be the same for all of these settings. the same is true for v3:v0 = 0010 through 0110. this means the device can be configured to translate between 74.175mhz, 74.25mhz, and 27mhz (from any one to another, all nine com- binations) and it will maintain the same loop response char- acteristics. this is also true for v3:v0 = 1000 through 1010. for high vcxo pll feedback divider values, the phase de- tector rate, and therefore loop filter charge pulse rate, is greatly reduced. to prevent output clock wander, low leakage capaci- tors should be used. in addition, when loop bandwidth is low (say below 20hz), capacitors with low microphonic sensitiv- ity should be used. pps film type capacitors are one type that perform well in this environment. below 5hz, shielding should be considered to prevent excessive phase wander (low fre- quency phase jitter or clock phase deviation). s etting the vcxo pll l oop r esponse the vcxo pll loop response is determined both by fixed device characteristics and by other characterizes set by the user. this includes the values of r s , c s , c p and r set as shown in the external vcxo pll components figure on this page. the vcxo pll loop bandwidth is approximated by: w here : r s = value of resistor r s in loop filter in ohms i cp = charge pump current in amps (see table on page 12) k o = vcxo gain in hz/v feedback divider = 1 to 11011 (as determined by inputs v3:v0) the above equation calculates the ?normalized? loop bandwidth (denoted as ?nbw?) which is approximately equal to the - 3db bandwidth. nbw does not take into account the effects of damping factor or the second pole imposed by c p . it does, however, provide a useful approximation of filter performance. to prevent jitter on the clock output due to modulation of the vcxo pll by the phase detector frequency, the following general rule should be observed: ? (phase detector) = input frequency pre-divider) the pll loop damping factor is determined by: w here : c s = value of capacitor c s in loop filter in farads nbw (vcxo pll) = r s x i cp x k o 2 x feedback divider nbw (vcxo pll) ? (phase detector) 20 df = x r s 2 i cp x c s x k o feedback divider
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 15 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary n otes on s etting the v alue of c p as another general rule, the following relationship should be maintained between components c s and c p in the loop filter: c p establishes a second pole in the vcxo pll loop filter. for higher damping factors (> 1), calculate the value of c p based on a c s value that would be used for a damping factor of 1. this will minimize baseband peaking and loop instability that can lead to output jitter. c p also dampens vcxo pll input voltage modulation by the charge pump correction pulses. a c p value that is too low will result in increased output phase noise at the phase detector frequency due to this. in extreme cases where input jitter is high, charge pump current is high, and c p is too small, the vcxo pll input voltage can hit the supply or ground rail resulting in non- linear loop response. the best way to set the value of c p is to use the filter response software available from ics (please refer to the following section). c p should be increased in value until it just starts affecting the passband peak. n otes on e xternal c rystal l oad c apacitors in the loop filter schematic diagram, capacitors are shown be- tween pins 27/30 to ground and between pins 38/31 to ground. these are optional crystal load capacitors which can be used to center tune the external pullable crystal (the crystal frequency can only be lowered by adding capacitance, it cannot be raised). note that the addition of external load capacitors will decrease the crystal pull range and the kvco value. l oop f ilter r esponse s oftware online tools to calculate loop filter response can be found at www .icst.com. contact your local sales representative if a tool cannot be found for this product. c p = c s 20 e xternal vcxo pll c omponents in general, the loop damping factor should be 0.7 or greater to ensure output stability. a higher damping factor will create less peaking in the passband. a higher damping factor may also increase lock time and output clock jitter when there is excess digital noise in the system application, due to the reduced ability of the pll to respond to and therefore compensate for phase noise ingress. 1 2 3 64 27/30 28/31 lf1 lf0 iset c s r s c p r set the external crystal devices and loop filter components should be kept close to the device. loop filter and crystal pcb connection traces should be kept short and well separated from each other and from other signal traces. other signal traces shouldnot run underneath the device, the loop filter or crystal components.
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 16 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary vcxo c rystal s election choosing a crystal with the correct characteristics is one of the most critical steps in using a voltage controlled crystal oscillator (vcxo). the crystal parameters affect the tuning range and v c control voltage used to tune frequency c v varactor capacitance, varies due to the change in control voltage c rystal p arameter e xamples l o b m y sr e t e m a r a pn o i t i d n o c t s e tl a c i p y tt i n u c w o l v e c n a t i c a p a c r o t c a r a v w o lv c v 0 =4 . 5 1f p c h g i h v e c n a t i c a p a c r o t c a r a v h g i hv c v 3 . 3 =6 . 9 2f p v aractor p arameters accuracy of a vcxo. below are the key variables and an example of using the crystal parameters to calculate the tuning range of the vcxo. c l1, c l2 load tuning capacitance used for fine tuning or centering nominal frequency c s1, c s2 stray capacitance caused by pads, vias, and other board parasitics oscillator f igure 1: vcxo o scillator c ircuit e xample vcxo (internal) c v c v c l1 c l2 optional c s1 c s2 v c ?control voltage? xtal l o b m y sr e t e m a r a pm u m i n i ml a c i p y tm u m i x a ms t i n u f n y c n e u q e r f l a n i m o n4 4 . 9 1z h m f t e c n a r e l o t y c n e u q e r f0 2 m p p f s y t i l i b a t s y c n e u q e r f0 2 m p p e g n a r e r u t a r e p m e t g n i t a r e p o00 7c c l e c n a t i c a p a c d a o l2 1f p c o e c n a t i c a p a c t n u h s4f p c 0 c / 1 o i t a r y t i l i b a l l u p0 2 20 4 2 r s ee c n a t s i s e r s e i r e s t n e l a v i u q e0 2 l e v e l e v i r d1w m c 5 2 @ g n i g ar a e y r e p 3 m p p n o i t a r e p o f o e d o ml a t n e m e d n u f
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 17 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary the example above will ensure a total pull range of 113.25 ppm with an apr of 58.25ppm. many times, board designers may select their own crystal based on their application. if the application requires a tighter apr, a crystal with better pullability f ormulas c low = (c l1 + c s1 + c v_low ) (c l2 + c s2 + c v_low ) (c l1 + c s1 + c v_low ) + (c l2 + c s2 + c v_low ) c high = (c l1 + c s1 + c v_high (c l2 + c s2 + c v_high ) (c l1 + c s1 + c v_high ) + (c l2 + c s2 + c v_high ) c low is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance. c low determines the high frequency component on the tpr (total pull range). c high is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance. c high determines the low frequency component on the tpr (total pull range). e xample c alculations using the tables and figures above, we can now calculate the tpr and apr of the vcxo using the example crystal parameters. for the numerical example below there were some assumptions made. first, the stray capacitance (c s1 , c s2 ), which is all the excess capacitance due to board parasitic, is 4pf. second, the expected lifetime of the project is 5 years; hence the inaccuracy due to aging is 15ppm. third, though many boards will not require load tuning capacitors (c l1 , c l2 ), it is recommended for long-term consistent performance of the system that two tuning capacitor pads be placed into every design. typical values for the load tuning capacitors will range from 0 to 4pf. absolutepullrange (apr) = totalpullrange ? (frequencytolerance + frequencystability + aging) tpr = 1 2 c 0 /c 1 (1+c low /c 0 ) 1 2 c 0 /c 1 (1+c high /c 0 ) ? 10 6 () c low = (0 + 4pf + 15.4pf) (0 + 4pf + 15.4pf) (0 + 4pf + 15.4pf) + (0 + 4pf + 15.4pf) = 9.7pf c high = (0 + 4pf + 29.6pf) (0 + 4pf + 29.6pf) (0 + 4pf + 29.6pf) + (0 + 4pf + 29.6pf) = 16.8pf tpr = 113.25ppm apr = 113.25ppm ? (20ppm + 20ppm + 15ppm) = 58.25ppm tpr = 1 2 220 (1+9.7pf/4pf) 1 2 220 (1+16.8pf/4pf) ? 10 6 = 226.5ppm () (c0/c1 ratio) can be used. also, with the equations above, one can vary the frequency tolerance, temperature stability, and aging or shunt capacitance to achieve the required pullability.
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 18 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ICS810001-21 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v dda , v ddx , and v ddo should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 3 illustrates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v dda pin. p ower s upply f iltering t echniques f igure 3. p ower s upply f iltering 10 v dda 10 f .01 f 3.3v .01 f v dd n otes on s etting c harge p ump c urrent the recommended range for the charge pump current is 50 a to 300 a. below 50 a, loop filter charge leakage, due to pcb or capacitor leakage, can become a problem. this loop filter leakage can cause locking problems, output clock cycle slips, or low frequency phase noise. 1e-3 100e-6 10e-6 1k 10k 100 k r set , i cp , amps r t e s i ( t n e r r u c p m u p e g r a h c p c ) k 6 . 7 1a 5 . 2 6 k 8 . 8a 5 2 1 k 4 . 4a 0 5 2 k 2 . 2a 0 0 5 f igure 2. c harge p ump c urrent vs . v alue of r set ( external resistor ) g raph as can be seen in the loop bandwidth and damping factor equations or by using the filter response software available from ics, increasing charge pump current (i cp ) increases both bandwidth and damping factor. c harge p ump c urrent , e xample s ettings
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 19 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary r eliability i nformation t ransistor c ount the transistor count for ICS810001-21 is: 9365 t able 7. ja vs . a ir f low t able for 32 l ead vfqfn ja vs. 0 air flow (linear feet per minute) 0 multi-layer pcb, jedec standard test boards 34. 8c/w
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 20 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary t able 8. p ackage d imensions p ackage o utline and d imensions - k s uffix for 32 l ead vfqfn reference document: jedec publication 95, mo-220 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s 2 - d h h v m u m i n i ml a n i m o nm u m i x a m n 2 3 a 0 8 . 0- -0 0 . 1 1 a 0- -5 0 . 0 3 a . f e r 5 2 . 0 b 8 1 . 05 2 . 00 3 . 0 n d 8 n e 8 d c i s a b 0 0 . 5 2 d 5 2 . 15 2 . 25 2 . 3 e c i s a b 0 0 . 5 2 e 5 2 . 15 2 . 25 2 . 3 e c i s a b 0 5 . 0 l 0 3 . 00 4 . 00 5 . 0
810001bk-21 www.icst.com/products/hiperclocks.html rev. a august 12, 2005 21 integrated circuit systems, inc. ICS810001-21 f emto c locks ? d ual vcxo v ideo pll preliminary t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without notice. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. the aforementioned trademarks, hiperclocks? and f emto c locks ? are a trademark of integrated circuit systems, inc. or its subsidiaries in the united states and/or other countries. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 1 2 - k b 1 0 0 0 1 8 s c i1 2 b 1 0 0 0 1 s c in f q f v d a e l 2 3y a r tc 0 7 o t c 0 t 1 2 - k b 1 0 0 0 1 8 s c i1 2 b 1 0 0 0 1 s c in f q f v d a e l 2 3l e e r & e p a t 0 0 5 2c 0 7 o t c 0

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